The invention is in the field of digital data systems, and relates more particularly to video graphic controllers for communicating with display devices.
Various FIFO buffer memories with read and write pointers, data wrapping and other underlying concepts used in the present invention are well known in the art. One example of such a FIFO buffer system is shown in U.S. Pat. No. 5,471,583, incorporated herein by reference in its entirety in order to explain many of the background concepts and components used in the present invention, in the interest of brevity. This reference, and other references such as U.S. Pat. No. 5,473,756, also directed to a FIFO buffer memory system, are directed to methods and apparatus for controlling such systems, and in particular for detecting full and/or empty states of the FIFO buffer in a more efficient manner in order to enhance speed of operation.
There exists, however, a particular situation in which the potential exists for a substantial improvement in prior-art video FIFO buffer performance. Video FIFO's, or screen-refresh FIFO's as they are sometimes referred to, are typically of very limited size and can hold only a fraction of an entire image. These FIFO's are constantly being filled from the memory side and emptied from the video output side. This can be seen in FIG. 1, which is an overview block diagram of a portion of a computer system. This figure shows the interconnection of a CPU 10, a memory system 12, peripherals such as a keyboard, mouse or printer 14 and a video graphics controller (VGC) 16 via an I/O chip set 19, a bridge chip set 21 and various associated lines and buses. With respect to the portion of the computer system relevant to the present invention, the video graphics controller 16 is coupled to a frame buffer memory (typically a DRAM) 18 and a display device 20 such as a CRT or flat-panel display. A digital video stream input is provided to the video graphics controller 16, as shown symbolically by the block 22 in FIG. 1. The FIFO memory is contained within the video graphics controller 16, as will be described in further detail hereinafter, and is filled from the frame buffer memory 18 and emptied to provide a signal for the display device 20.
Prior-art FIG. 2 shows a portion of the video graphics controller 16 in further detail. This figure shows, in overview form, a portion of the video graphics controller having an SRAM cache used as a FIFO memory and designated with the reference numeral 100. A memory controller 102 looks at the volume of the SRAM 100 by comparing the read and write pointers, 104 and 106, respectively, derived at the output of a subtractor 108, with the difference being applied to the memory controller 102. When the volume of the memory, as represented by the output of subtractor 108, reaches a level such that more information must be put in, the memory controller bursts enough information to fill the FIFO and then resumes its other tasks. Meanwhile, the display device 20 is being refresh by a slow drain of data from the FIFO, with the read pointer being incremented for every piece of data used, and with the incrementing of the pointers being shown symbolically by the blocks labeled +1 in FIG. 2. When the read pointer equals the write pointer, the FIFO is empty. Since the system as so far described is known in the prior art, and is similar in general configuration to that shown in U.S. Pat. No. 5,471,583, it will not be described in further detail herein.
As noted above, video FIFO's are typically very limited in size, and are constantly being filled from the memory side and emptied from the video output side. However, under certain conditions, such as when an image can fit entirely within the video FIFO memory, where there is no need to keep filling the FIFO from the memory side unless the image to be displayed has been altered. An example of such a situation occurs with a typical mouse cursor, wherein the SRAM FIFO memory capacity is large enough to hold the entire image, and wherein there are times during which the image remains static.
Since the frame buffer DRAM 18 has substantially greater capacity than that needed to hold the cursor image, and since the path between the frame buffer 18 and the video graphics controller 16 is typically single ported (i.e., only one read or write operation to a single location may take place at any point in time) this portion of the system must have a greater bandwidth than that required by the display refresh stream alone, and the path must be time-multiplexed. The relatively small memory array in the video graphics controller is used to equalize the fast periodic burst of data from the frame buffer memory and is typically configured as an SRAM (100) organized as a circular buffer and used as a FIFO. Under these conditions, system performance could be substantially improved by reducing the bandwidth required to refresh the display under proper circumstances, such as the presence of a small, frequently unchanging image such as that of a mouse cursor.